15.03.15 - 20.03.15, Seminar 15121

Mixed Criticality on Multicore/Manycore Platforms

Diese Seminarbeschreibung wurde vor dem Seminar auf unseren Webseiten veröffentlicht und bei der Einladung zum Seminar verwendet.


The objective of this seminar is to bring together researchers working in fields relating to real-time systems to promote understanding of the fundamental problems affecting Mixed Criticality Systems (MCS) at all levels in the software/hardware stack and, crucially, the interfaces between them. A specific focus will be the challenges brought about by the integration of mixed criticality applications onto multi-core and many-core architectures. As these challenges cut across communities and disciplines, the sub-communities involved in real-time scheduling, real-time operating systems / runtime environments, and timing analysis (WCET) must interact more closely with each other and with specialists in hardware architectures if they are to advance rapidly. To that end, the seminar seeks to promote a lively interaction, synergies, cross-fertilization of ideas, and closer collaboration across the breadth of the real-time community.

Key research questions to be addressed include:

  • How to provide effective guarantees of real-time performance to applications of different criticality levels via intelligent sharing of resources while respecting the requirements for asymmetric separation / isolation between criticality levels?
  • How to provide asymmetric time separation between applications with different levels of criticality so that the impact of lower criticality applications on those of higher criticality can be tightly bounded independently of the behavior or misbehavior of the former, without significantly compromising guaranteed real-time performance?
  • How to provide time composability for applications of different criticality levels, so that the timing behavior of applications determined in isolation remains valid when they are composed during system integration?

The seminar will crucially span from the low level behavior of the memory hierarchy, and network-on-chip or buses, through timing analysis that includes delays due to shared resources (e.g. cache-related or migration delays), real-time operating system behavior, and high level scheduling, and task allocation to the verification of end-to-end deadlines.

Seminar sessions will be structured around the following key themes and will pay particular attention to the interfaces between themes, as these are the areas that can most benefit from improved understanding and collaboration:

  • Task and system models for MCS on multi-core and many-core platforms.
  • Scheduling schemes and analyses for MCS, including the integration of appropriate models of overheads and delays.
  • Run-time environments and support for MCS, including data exchange and synchronization across criticality levels, and issues relating to consistency of the criticality mode.
  • Analysis of worst-case execution times relating to MCS on multi-core and many-core platforms, including cache related and migration delays.
  • Mixed criticality communications mechanisms and analysis, including Network-on-Chip support.
  • Probabilistic analysis techniques for MCS.

The seminar does not intend to cover security issues that relate to some MCS. While it aims to be cognisant of the needs for certification in some industries, the seminar also does not seek to address the certification process.

As with other Dagstuhl Seminars, this seminar will provide open forum for discussion without program selection or review.