Semiconductor technology has advanced so fast in the last decade such that the integration of 100s of processor cores on a single device is reality and not fiction. Today, extremely resource and energy efficient multi-processor system-on-a-chip (MPSoC) architectures have been proposed in terms of so-called processor array SoC designs. These are ideal candidates for energy-efficient processing of loop programs as they provide a natural match for loop-level parallelism, combined with instruction-level and word-level parallelism. Such computing arrays include the classes CGRAs (coarse-grained reconfigurable arrays) and TCPAs (tightly coupled processor arrays). The demand for such “kilocore processor arrays” is driven by many applications such as linear algebra, signal and image processing, and mostly by deep learning. In comparison to GPUs, on-chip computing arrays can provide several orders of magnitude higher energy efficiency margins of Giga-to-Tera operations per second and Watt (e.g., TFLOPs/W). However, architectural design decisions are not effective unless compilation and mapping tools can leverage such decisions, and unless optimization techniques for configuration and program code exploit such architecture artifacts to the best possible extent.

This Dagstuhl seminar wants to bring together experts for On-Chip (Re-)configurable computing array architectures to discuss scope, support, and limitations of current architectures and compilers. This includes designers, compiler developers, and practitioners. The first focus for interdisciplinary discussions shall be the qualitative analysis of approaches regarding scope and generality/degree of specialization. A second focus shall be put on quantitative evaluation. Here, techniques allowing a technology-independent comparison of different architecture/compiler toolchains shall be elaborated. The latter requires the definition and agreement on a common benchmarking approach to allow objective comparison among different architectures/compilers. The third focus of the seminar will be a study of limits and bottlenecks of programmable processor array designs including memory, core count, or bandwidth limitations and how to deal with these systematically.

We aim to build a network committed to designing processor array architectures and related compilation and mapping techniques, and to lay foundations for the common understanding and benchmarking of such architectures.

Creative Commons BY 4.0

Jason H. Anderson, Laura Pozzi, Kentaro Sano, and Jürgen Teich