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Dagstuhl-Seminar 9249

Self-Timed Design

( 30. Nov – 04. Dec, 1992 )

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  • F.J. Rammig
  • G. Zimmermann
  • J. Staunstrup


Self-timed circuits have potential performance benefits compared to synchronous circuits. Because of their delay insensitivity and the absence of a clock every part of a circuit can work as fast as possible without violating constraints based on worst case assumptions. Self-timed circuits also have the benefit of potentially very low power consumption and a very wide range of operating temperatures and supply voltages. The disadvantage is the additional chip area necessary and the difficulty of the design. Very little practical experience exists to support the made claims on benefits or disadvantages and synthesis techniques are just evolving.

Self-timed circuits require design methods and CAD tools which are different from the ones used for synchronous circuits. Furthermore, a lot of the accumulated experience with designing synchronous circuits is not appropriate, for example approaches based on a finite state machine controlling the computation. To take advantage of the potential benefits, it is important to find design techniques which make it feasible to design reliable and efficient circuits with reasonable effort.

This seminar therefore brought together participants with an active interest and good background in the field of self-timed circuits with participants from related fields of design. The participants had been asked ahead of time to provide the organizers with a list of up to five topics that they would like to see discussed at the seminar. Participants had been discouraged to present known work or give "sales talks" advocating ones own results.

The answers could be combined to three major topics of general interest and the following descriptions of the topics were sent to the participants together with five examples provided by Jo C. Ebergen

  • Synthesis
    Synthesis of self-timed circuits from hi gh-level descriptions is an important topic. To stimulate discussion and evaluation of the synthesis techniques a small set of design problems are given to all participants. The organizers want to encourage anybody wishing to give a presentation on synthesis to use one or more of these examples to illustrate their technique. The problems are provided by Jo Ebergen.
  • Cost/ performance
    The literature is full of claims about properties. advantages and disadvantages of self-timing. It would be nice to collect documentation for these claims. Presentations are invited from participants who can provide evidence for quantitative properties such as, speed, power consumption, area, etc.
  • Delay (in-) sensitivity: how much?
    It appears that absolutely delay-insensitive circuits are of little or no practical value. Therefore, all published designs are based on some assumptions about delays typically in isochronic forks. This immediately raises the question of how to trade off delay assumptions against other properties. Participants are invited to present contributions that can illuminate this issue. A detailed description of the examples can be found on page 5 of the Dagstuhl-Seminar-Report.

The seminar fulfilled the expectations in so far as it was dominated by discussions on the proposed topics that were triggered by a relatively small number of presentations. The exercises turned out to be well accepted and focused the discussion about design methods in an excellent way.

The seminar did not completely answer any of the questions. Surprising for most of the participants was the fact that more real examples of self-timed systems existed than previously assumed and a collection of references was started. Some discussions went back to the fundamental question of the construction of a reliable orbiter which still does not seen to be answered. In general the discussion showed that much progress towards design methods has been made recently but much more effort is still necessary. What could be a better result for research?


  • F.J. Rammig
  • G. Zimmermann
  • J. Staunstrup