The size and complexity of present day VLSI integrated circuits (IC) and systems demands the elimination of repetitive manual operations and computations in their design.This motivates the development of automatic design systems. Automation of a given(design)process requires its algorithmic analysis.The availability of fast and easily implementable algorithms is essential for the discipline, as heuristic techniques and ad hoc approaches,by themselves,cannot cope with the complexity of current(and future) IC systems.Indeed, IC designers are forced to employ algorithmic techniques and systematic approaches to design fast and reliable VLSI circuits.

The objective of this workshop was to bring together researchers whose common grounds are that they have an understanding of algorithm design, combinatorial structures,and graph theory and are interested in VLSI applications. These researchers either have been working on IC design and are applying algorithmic techniques in order to cope with the complexity of VLSI systems.Or theyhavebeenworkingonalgorithmicgraphtheoryandcombinatoricsandhave found a new source of problems in VLSI domain. A focus of the workshop was on physical design, since this is the part of IC design that encompasses the most challenging applications of combinatorial algorithms

The purpose of this workshop was to further investigate practical VLSI models, address important and relevant issues, and to apply recent developments in algorithm design and combinatorial structures to VLSI problems. One goal was to develop models that accurately practical practical issues and thus generalize some of the models currently being used. Corresponding problems need to be formulated without sacrificing their realistic nature.

During the workshop 25 lectures have been presented by the participants from different European countries, U.S.A., Japan, Taiwan and Korea.The lectures covered various topics from graph algorithms and combinatorics,e.g. Steiner trees and disjoint paths problems, cut and partitioning problems,and WQO based methods, as well as subjects from practical design as FPGA technology mapping, global optimization for practical VLSI problems and different layout systems. There were two problem sessions and an evening discussion on the Interaction between Theory and Practice in Physical Design.

All participants appreciated the stimulating and cordial atmosphere at Schloß Dagstuhl. The always engaged support of the Dagstuhl team was an essential contribution to the success of this seminar.

The organizers wish to thank all those who helped make the workshop an interesting and fruitful research experience.

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