http://www.dagstuhl.de/13172

21. – 24. April 2013, Event 13172

NSF/SRC/DFG Joint Workshop on “Bugs and Defects in Electronic Systems: the Next Frontier”

Organisatoren

Wolfgang Kunz (TU Kaiserslautern, DE)
Subhasish Mitra (Stanford University, US)

Auskunft zu diesem Event erteilt

Heike Clemens

Dokumente

Gemeinsame Dokumente

Motivation

This workshop brings together US and German scientific communities from the research areas of Design Verification, Formal Methods, Manufacturing Testing, Robust System Design, Security, and related areas of micro and nano electronic design automation. The larger objective is to explore possibilities of long term future collaboration between the two communities in the context of basic research. However, for the immediate future the workshop will start by discussing major upcoming obstacles in the design, verification, and testing of robust systems. Pre-silicon verification is insufficiently scalable, and scan-based manufacturing testing may not be adequate in screening marginal and reliability failures. Moving forward, bugs and defects that impact system correctness and/or security must be detected, localized, and corrected in the system environment, during post-silicon validation, or during system operation in the field. While some ad-hoc approaches to address these challenges are starting to appear in specific design domains, there is an immediate need for systematic design methodologies to overcome these challenges in general system designs. These needed methodologies mark a radical departure from today’s practice and require a multi-disciplinary effort spanning the traditionally distinct research areas stated above.

The workshop participants will articulate the overall challenge with emphasis on specific focus areas that require significant research. In addition to individual presentations, the attendees will work together to produce a workshop report identifying critical research needs: from new research ideas to benchmarking techniques to quantify the pros and cons of new ideas. A joint initiative of NSF, SRC, and DFG, this workshop will use the technical topic as a means to assess the value of joint collaborations between the US and German research communities and explore various collaboration mechanisms that can be supported by the involved funding agencies.

Scope

Hardware failures are a growing concern as electronic systems become more complex, interconnected, and pervasive. Existing test and validation methods barely cope with today’s system complexity, which continues to rise as electronic systems continue to integrate more and more (heterogeneous) components to target a wide variety of critical applications such as health care, transportation, energy, finance and governance. For coming generations of silicon ICs with remarkably small geometries, several failure mechanisms, largely benign in the past, are becoming visible at the system-level. Finally, improving energy efficiency of electronic systems in the absence of Dennard scaling comes at the price of significant complexity: increasing amounts of cores, uncore components, and accelerators; increasing degrees of adaptivity; and increasing levels of heterogeneous integration. These trends make future systems highly vulnerable to errors that can jeopardize correct operation, cause early-life failures, or introduce security vulnerabilities. Such effects are already visible in today’s systems resulting in significant product shipment delays and product recalls.

We need a radical departure from business as usual. The premise of this workshop is:

  1. Traditional pre-silicon verification is no longer sufficient for weeding out design bugs. These include both “logic” bugs and “electrical” bugs. Post-silicon validation (before high-volume manufacturing) and in-field techniques (after shipment) are required to detect, localize, and fix design bugs.
  2. Traditional scan-based testing will not be adequate in screening failures related to circuit marginality and reliability. Such failures must be detected, diagnosed, and fixed during system-level testing (before shipment) or during system operation in the field.

To cope with these outstanding challenges, the scope of traditional test and validation must be significantly broadened. This requires a major rethinking: how to think about new cross-layer methodologies, spanning multiple abstraction layers from circuit design all the way to software, to overcome the major roadblocks. This objective cannot be achieved without investigating the scientific foundations underlying current and future technologies and a collaborative effort across traditionally distinct research communities: design verification, manufacturing testing, reliable and adaptive system design, formal methods, and security to name a few. Another highly important aspect of such a collaborative effort is the creation of a new set of benchmarks that can drive quantitative evaluation of new techniques. Such benchmarks are crucial to quickly achieve significant technical progress in this emerging field.

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