http://www.dagstuhl.de/00261

June 25 – 30 , 2000, Dagstuhl Seminar 00261

Dynamically Reconfigurable Architectures

Organizers

G. Brebner (Edinburgh), K.-H. Brenner (Mannheim), H. ElGindy (Newcastle, AUS), H. Schmeck (Karlsruhe)


The Dagstuhl Foundation gratefully acknowledges the donation from:

  • Xilinx Inc., San Jose

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Dagstuhl Service Team

Documents

External Homepage
Dagstuhl-Seminar-Report 279

This seminar will be a continuation of the first Dagstuhl seminar on "Dynamically Reconfigurable Architectures" in February 1998 which has been a very successful meeting of people from different research areas - algorithms, hardware, and optical communication. The seminar showed that technological advances have opened up new ways of implementing complex systems in a way blurring the barriers between hardware and software components development, and that existing design tools do not seem to be adequate for the necessary new design styles. Furthermore, new advances in optical communication lead to feasible implementations of interconnection structures which so far had been seen as having only theoretical value.

The fast pace of development in industry is leaving no time to develop the necessary theoretical foundation that underpins CAD tools, operating systems, designs. A typical example is the discontinuation of the very promising and truly dynamically reconfigurable XC6200-series.

Traditional hardware and software design processes and the tools to support them are not adequate for the design of systems which can be reconfigured dynamically, recently also called "run time reconfigurable" systems. Therefore, the plan for this seminar is to focus on the issues relevant to the development of support for the RTR technologies.

That will cover: device architecture, system architecture, tools for RTR, general/special purpose systems, and of course applications/algorithms/designs.

We also think that the challenges posed by integrating optical technology with dynamically reconfigurable architectures should remain an important part of this seminar. Finally, we are interested in the use of dynamically reconfigurable architectures for implementing and experimenting with evolvable hardware.

Some key questions to be addressed are:

  1. What are shared characteristics of, and possible interfaces between, machine-based computational models and circuit-based computational models?
  2. How will current "ASIC replacement" device architectures evolve to be genuine "computational component" device architectures?
  3. What are appropriate system-level architectures for systems composed of processors, configurable logic and memory, and how might these be implemented at chip level?
  4. What overall computational models are best to evaluate alternative system-level architectures?
  5. Which aspects of current hardware and software design practice are, and are not, relevant to the design of "soft" circuitry and "hard" programs?
  6. What are appropriate new design processes, and supporting tools, for systems composed of a mixture of circuit and program, implemented in hard and soft manners?
  7. How general purpose can system design be? Is specialisation inevitable to achieve best performance?
  8. How are reconfigurable systems best presented to algorithm designers?
  9. What are realistic aspirations for the practical benefits achievable from the use of reconfigurable systems?
  10. How can optical communication be used best to support RTR?

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