Volume
LIPIcs, Volume 133
31st Euromicro Conference on Real-Time Systems (ECRTS 2019)
-
Part of:
Series:
Leibniz International Proceedings in Informatics (LIPIcs)
Conference: Euromicro Conference on Real-Time Systems (ECRTS)
Event
ECRTS 2019, July 9-12, 2019, Stuttgart, GermanyEditor
Publication Details
- published at: 2019-07-02
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- ISBN: 978-3-95977-110-8
- DBLP: db/conf/ecrts/ecrts2019
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Document
Complete Volume
LIPIcs, Volume 133, ECRTS'19, Complete Volume
Abstract
LIPIcs, Volume 133, ECRTS'19, Complete Volume
Cite as
31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@Proceedings{quinton:LIPIcs.ECRTS.2019,
title = {{LIPIcs, Volume 133, ECRTS'19, Complete Volume}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019},
URN = {urn:nbn:de:0030-drops-107744},
doi = {10.4230/LIPIcs.ECRTS.2019},
annote = {Keywords: Computer systems organization, Embedded and cyber-physical systems, Computer systems organization, Real-time systems, Software and its engineering}
}
Document
Front Matter
Front Matter, Table of Contents, Preface, Conference Organization
Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as
31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 0:i-0:xi, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{quinton:LIPIcs.ECRTS.2019.0,
author = {Quinton, Sophie},
title = {{Front Matter, Table of Contents, Preface, Conference Organization}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {0:i--0:xi},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.0},
URN = {urn:nbn:de:0030-drops-107377},
doi = {10.4230/LIPIcs.ECRTS.2019.0},
annote = {Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
DMAC: Deadline-Miss-Aware Control
Abstract
The real-time implementation of periodic controllers requires solving a co-design problem, in which the choice of the controller sampling period is a crucial element. Classic design techniques limit the period exploration to safe values, that guarantee the correct execution of the controller alongside the remaining real-time load, i.e., ensuring that the controller worst-case response time does not exceed its deadline. This paper presents DMAC: the first formally-grounded controller design strategy that explores shorter periods, thus explicitly taking into account the possibility of missing deadlines. The design leverages information about the probability that specific sub-sequences of deadline misses are experienced. The result is a fixed controller that on average works as the ideal clairvoyant time-varying controller that knows future deadline hits and misses. We obtain a safe estimate of the hit and miss events using the scenario theory, that allows us to provide probabilistic guarantees. The paper analyzes controllers implemented using the Logical Execution Time paradigm and three different strategies to handle deadline miss events: killing the job, letting the job continue but skipping the next activation, and letting the job continue using a limited queue of jobs. Experimental results show that our design proposal - i.e., exploring the space where deadlines can be missed and handled with different strategies - greatly outperforms classical control design techniques.
Cite as
Paolo Pazzaglia, Claudio Mandrioli, Martina Maggio, and Anton Cervin. DMAC: Deadline-Miss-Aware Control. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 1:1-1:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{pazzaglia_et_al:LIPIcs.ECRTS.2019.1,
author = {Pazzaglia, Paolo and Mandrioli, Claudio and Maggio, Martina and Cervin, Anton},
title = {{DMAC: Deadline-Miss-Aware Control}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {1:1--1:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.1},
URN = {urn:nbn:de:0030-drops-107387},
doi = {10.4230/LIPIcs.ECRTS.2019.1},
annote = {Keywords: Weakly-Hard Real-Time Systems, Deadline Miss Handling, Control Design}
}
Document
Control-Flow Integrity for Real-Time Embedded Systems
Abstract
Attacks on real-time embedded systems can endanger lives and critical infrastructure. Despite this, techniques for securing embedded systems software have not been widely studied. Many existing security techniques for general-purpose computers rely on assumptions that do not hold in the embedded case. This paper focuses on one such technique, control-flow integrity (CFI), that has been vetted as an effective countermeasure against control-flow hijacking attacks on general-purpose computing systems. Without the process isolation and fine-grained memory protections provided by a general-purpose computer with a rich operating system, CFI cannot provide any security guarantees. This work proposes RECFISH, a system for providing CFI guarantees on ARM Cortex-R devices running minimal real-time operating systems. We provide techniques for protecting runtime structures, isolating processes, and instrumenting compiled ARM binaries with CFI protection. We empirically evaluate RECFISH and its performance implications for real-time systems. Our results suggest RECFISH can be directly applied to binaries without compromising real-time performance; in a test of over six million realistic task systems running FreeRTOS, 85% were still schedulable after adding RECFISH.
Cite as
Robert J. Walls, Nicholas F. Brown, Thomas Le Baron, Craig A. Shue, Hamed Okhravi, and Bryan C. Ward. Control-Flow Integrity for Real-Time Embedded Systems. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 2:1-2:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{walls_et_al:LIPIcs.ECRTS.2019.2,
author = {Walls, Robert J. and Brown, Nicholas F. and Le Baron, Thomas and Shue, Craig A. and Okhravi, Hamed and Ward, Bryan C.},
title = {{Control-Flow Integrity for Real-Time Embedded Systems}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {2:1--2:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.2},
URN = {urn:nbn:de:0030-drops-107397},
doi = {10.4230/LIPIcs.ECRTS.2019.2},
annote = {Keywords: Control-flow integrity}
}
Document
Simultaneous Multithreading Applied to Real Time
Abstract
Existing models used in real-time scheduling are inadequate to take advantage of simultaneous multithreading (SMT), which has been shown to improve performance in many areas of computing, but has seen little application to real-time systems. The SMART task model, which allows for combining SMT and real time by accounting for the variable task execution costs caused by SMT, is introduced, along with methods and conditions for scheduling SMT tasks under global earliest-deadline-first scheduling. The benefits of using SMT are demonstrated through a large-scale schedulability study in which we show that task systems with utilizations 30% larger than what would be schedulable without SMT can be correctly scheduled.
Cite as
Sims Hill Osborne, Joshua J. Bakita, and James H. Anderson. Simultaneous Multithreading Applied to Real Time. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 3:1-3:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{osborne_et_al:LIPIcs.ECRTS.2019.3,
author = {Osborne, Sims Hill and Bakita, Joshua J. and Anderson, James H.},
title = {{Simultaneous Multithreading Applied to Real Time}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {3:1--3:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.3},
URN = {urn:nbn:de:0030-drops-107400},
doi = {10.4230/LIPIcs.ECRTS.2019.3},
annote = {Keywords: real-time systems, simultaneous multithreading, soft real-time, scheduling algorithms}
}
Document
PREM-Based Optimal Task Segmentation Under Fixed Priority Scheduling
Abstract
Recently, a large number of works have discussed scheduling tasks consisting of a sequence of memory phases, where code and data are moved between main memory and local memory, and computation phases, where the task executes based on the content of local memory only; the key idea is to prevent main memory contention by scheduling the memory phase of one task in parallel with computation phases of tasks running on other cores. This paper provides two main contributions: (1) we present a compiler-level tool, based on the LLVM intermediate representation, that automatically converts a program into a conditional sequence of segments comprising memory and computation phases; (2) we propose an algorithm to find optimal segmentation decisions for a task set scheduled according to a fixed-priority partitioned scheme. Our evaluation shows that the proposed framework can be feasibly applied to realistic programs, and vastly overperforms a baseline greedy approach.
Cite as
Muhammad R. Soliman and Rodolfo Pellizzoni. PREM-Based Optimal Task Segmentation Under Fixed Priority Scheduling. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 4:1-4:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{soliman_et_al:LIPIcs.ECRTS.2019.4,
author = {Soliman, Muhammad R. and Pellizzoni, Rodolfo},
title = {{PREM-Based Optimal Task Segmentation Under Fixed Priority Scheduling}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {4:1--4:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.4},
URN = {urn:nbn:de:0030-drops-107417},
doi = {10.4230/LIPIcs.ECRTS.2019.4},
annote = {Keywords: PREM, LLVM, scratchpad memory, scheduling, program segmentation}
}
Document
RT-CASEs: Container-Based Virtualization for Temporally Separated Mixed-Criticality Task Sets
Abstract
This paper presents the notion of real-time containers, or rt-cases, conceived as the convergence of container-based virtualization technologies, such as Docker, and hard real-time operating systems. The idea is to allow critical containers, characterized by stringent timeliness and reliability requirements, to cohabit with traditional non real-time containers on the same hardware. The approach allows to keep the advantages of real-time virtualization, largely adopted in the industry, while reducing its inherent scalability limitation when to be applied to large-scale mixed-criticality systems or severely constrained hardware environments. The paper provides a reference architecture scheme for implementing the real-time container concept on top of a Linux kernel patched with a hard real-time co-kernel, and it discusses a possible solution, based on execution time monitoring, to achieve temporal separation of fixed-priority hard real-time periodic tasks running within containers with different criticality levels. The solution has been implemented using Docker over a Linux kernel patched with RTAI. Experimental results on real machinery show how the implemented solution is able to achieve temporal separation on a variety of random task sets, despite the presence of faulty tasks within a container that systematically exceed their worst case execution time.
Cite as
Marcello Cinque, Raffaele Della Corte, Antonio Eliso, and Antonio Pecchia. RT-CASEs: Container-Based Virtualization for Temporally Separated Mixed-Criticality Task Sets. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 5:1-5:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{cinque_et_al:LIPIcs.ECRTS.2019.5,
author = {Cinque, Marcello and Della Corte, Raffaele and Eliso, Antonio and Pecchia, Antonio},
title = {{RT-CASEs: Container-Based Virtualization for Temporally Separated Mixed-Criticality Task Sets}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {5:1--5:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.5},
URN = {urn:nbn:de:0030-drops-107426},
doi = {10.4230/LIPIcs.ECRTS.2019.5},
annote = {Keywords: Containers, mixed-criticality, temporal separation, monitoring}
}
Document
Response-Time Analysis of ROS 2 Processing Chains Under Reservation-Based Scheduling
Abstract
Bounding the end-to-end latency of processing chains in distributed real-time systems is a well-studied problem, relevant in multiple industrial fields, such as automotive systems and robotics. Nonetheless, to date, only little attention has been given to the study of the impact that specific frameworks and implementation choices have on real-time performance. This paper proposes a scheduling model and a response-time analysis for ROS 2 (specifically, version "Crystal Clemmys" released in December 2018), a popular framework for the rapid prototyping, development, and deployment of robotics applications with thousands of professional users around the world. The purpose of this paper is threefold. Firstly, it is aimed at providing to robotic engineers a practical analysis to bound the worst-case response times of their applications. Secondly, it shines a light on current ROS 2 implementation choices from a real-time perspective. Finally, it presents a realistic real-time scheduling model, which provides an opportunity for future impact on the robotics industry.
Cite as
Daniel Casini, Tobias Blaß, Ingo Lütkebohle, and Björn B. Brandenburg. Response-Time Analysis of ROS 2 Processing Chains Under Reservation-Based Scheduling. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 6:1-6:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{casini_et_al:LIPIcs.ECRTS.2019.6,
author = {Casini, Daniel and Bla{\ss}, Tobias and L\"{u}tkebohle, Ingo and Brandenburg, Bj\"{o}rn B.},
title = {{Response-Time Analysis of ROS 2 Processing Chains Under Reservation-Based Scheduling}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {6:1--6:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.6},
URN = {urn:nbn:de:0030-drops-107431},
doi = {10.4230/LIPIcs.ECRTS.2019.6},
annote = {Keywords: ROS, real-time systems, response-time analysis, robotics, resource reservation}
}
Document
Implementation of Memory Centric Scheduling for COTS Multi-Core Real-Time Systems
Abstract
The demands for high performance computing with a low cost and low power consumption are driving a transition towards multi-core processors in many consumer and industrial applications. However, the adoption of multi-core processors in the domain of real-time systems faces a series of challenges that has been the focus of great research intensity during the last decade. These challenges arise in great part from the non real-time nature of the hardware arbiters that schedule the access to shared resources, such as the main memory. One solution proposed in the literature is called Memory Centric Scheduling, which defines a separate software scheduler for the sections of the tasks that will access the main memory, hence circumventing the low level unpredictable hardware arbiters. Several Memory Centric schedulers and associated theoretical analyses have been proposed, but as far as we know, no actual implementation of the required OS-level underpinnings to support dynamic event-driven Memory Centric Scheduling has been presented before. In this paper we aim to fill this gap, targeting cache based COTS multi-core systems. We will confirm via measurements the main theoretical benefits of Memory Centric Scheduling (e.g. task isolation). Furthermore, we will describe an effective schedulability analysis using concepts from distributed systems.
Cite as
Juan M. Rivas, Joël Goossens, Xavier Poczekajlo, and Antonio Paolillo. Implementation of Memory Centric Scheduling for COTS Multi-Core Real-Time Systems. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 7:1-7:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{rivas_et_al:LIPIcs.ECRTS.2019.7,
author = {Rivas, Juan M. and Goossens, Jo\"{e}l and Poczekajlo, Xavier and Paolillo, Antonio},
title = {{Implementation of Memory Centric Scheduling for COTS Multi-Core Real-Time Systems}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {7:1--7:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.7},
URN = {urn:nbn:de:0030-drops-107448},
doi = {10.4230/LIPIcs.ECRTS.2019.7},
annote = {Keywords: real-time, multi-core, memory centric, predictability, implementation, rtos}
}
Document
Industrial Application of a Partitioning Scheduler to Support Mixed Criticality Systems
Abstract
The ever-growing complexity of safety-critical control systems continues to require evolution in control system design, architecture and implementation. At the same time the cost of developing such systems must be controlled and importantly quality must be maintained.
This paper examines the application of Mixed Criticality System (MCS) research to a DAL-A aircraft engine Full Authority Digital Engine Control (FADEC) system which includes studying porting the control system’s software to a preemptive scheduler from a non-preemptive scheduler. The paper deals with three key challenges as part of the technology transitions. Firstly, how to provide an equivalent level of fault isolation to ARINC 653 without the restriction of strict temporal slicing between criticality levels. Secondly extending the current analysis for Adaptive Mixed Criticality (AMC) scheduling to include the overheads of the system. Finally the development of clustering algorithms that automatically group tasks into larger super-tasks to both reduce overheads whilst ensuring the timing requirements, including the important task transaction requirements, are met.
Cite as
Stephen Law, Iain Bate, and Benjamin Lesage. Industrial Application of a Partitioning Scheduler to Support Mixed Criticality Systems. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 8:1-8:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{law_et_al:LIPIcs.ECRTS.2019.8,
author = {Law, Stephen and Bate, Iain and Lesage, Benjamin},
title = {{Industrial Application of a Partitioning Scheduler to Support Mixed Criticality Systems}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {8:1--8:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.8},
URN = {urn:nbn:de:0030-drops-107455},
doi = {10.4230/LIPIcs.ECRTS.2019.8},
annote = {Keywords: MCS, DO-178C, Real-Time}
}
Document
From Iteration to System Failure: Characterizing the FITness of Periodic Weakly-Hard Systems
Abstract
Estimating metrics such as the Mean Time To Failure (MTTF) or its inverse, the Failures-In-Time (FIT), is a central problem in reliability estimation of safety-critical systems. To this end, prior work in the real-time and embedded systems community has focused on bounding the probability of failures in a single iteration of the control loop, resulting in, for example, the worst-case probability of a message transmission error due to electromagnetic interference, or an upper bound on the probability of a skipped or an incorrect actuation. However, periodic systems, which can be found at the core of most safety-critical real-time systems, are routinely designed to be robust to a single fault or to occasional failures (case in point, control applications are usually robust to a few skipped or misbehaving control loop iterations). Thus, obtaining long-run reliability metrics like MTTF and FIT from single iteration estimates by calculating the time to first fault can be quite pessimistic. Instead, overall system failures for such systems are better characterized using multi-state models such as weakly-hard constraints. In this paper, we describe and empirically evaluate three orthogonal approaches, PMC, Mart, and SAp, for the sound estimation of system’s MTTF, starting from a periodic stochastic model characterizing the failure in a single iteration of a periodic system, and using weakly-hard constraints as a measure of system robustness. PMC and Mart are exact analyses based on Markov chain analysis and martingale theory, respectively, whereas SAp is a sound approximation based on numerical analysis. We evaluate these techniques empirically in terms of their accuracy and numerical precision, their expressiveness for different definitions of weakly-hard constraints, and their space and time complexities, which affect their scalability and applicability in different regions of the space of weakly-hard constraints.
Cite as
Arpan Gujarati, Mitra Nasri, Rupak Majumdar, and Björn B. Brandenburg. From Iteration to System Failure: Characterizing the FITness of Periodic Weakly-Hard Systems. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 9:1-9:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{gujarati_et_al:LIPIcs.ECRTS.2019.9,
author = {Gujarati, Arpan and Nasri, Mitra and Majumdar, Rupak and Brandenburg, Bj\"{o}rn B.},
title = {{From Iteration to System Failure: Characterizing the FITness of Periodic Weakly-Hard Systems}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {9:1--9:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.9},
URN = {urn:nbn:de:0030-drops-107468},
doi = {10.4230/LIPIcs.ECRTS.2019.9},
annote = {Keywords: reliability analysis, MTTF/FIT analysis, weakly-hard constraints}
}
Document
End-To-End Deadlines over Dynamic Topologies
Abstract
Despite the creativity of the scientific community and the funding agencies, the underlying model of computation behind IoT, WSN, cloud, edge, fog, and mist is fundamentally the same; Computational nodes which are dynamically interconnected to form a system in where both processing capacity and connectivity may vary over time. On top of such a system, we consider applications that need packets to flow along a path and adhere to end-to-end deadlines. This application model is motivated by both control and automation systems, as well as telecom systems. The challenge is to guarantee end-to-end deadlines when allowing nodes and applications to join or leave.
The mainstream, and to some extent natural, approach to this is to relax the stringency of the constraint (e.g. use probabilistic guarantees, soft deadlines). In this paper we take a different approach and keep the end-to-end deadlines as hard constraints and instead partially limit the freedom of how nodes and applications are allowed to leave and join. We present a theoretical framework for modeling such systems along with proofs that deadlines are always honored.
Cite as
Victor Millnert, Johan Eker, and Enrico Bini. End-To-End Deadlines over Dynamic Topologies. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 10:1-10:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{millnert_et_al:LIPIcs.ECRTS.2019.10,
author = {Millnert, Victor and Eker, Johan and Bini, Enrico},
title = {{End-To-End Deadlines over Dynamic Topologies}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {10:1--10:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.10},
URN = {urn:nbn:de:0030-drops-107473},
doi = {10.4230/LIPIcs.ECRTS.2019.10},
annote = {Keywords: Cloud, real-time, end-to-end latency guarantee, end-to-end response time guarantee, dynamic network}
}
Document
Reliable Dynamic Packet Scheduling over Lossy Real-Time Wireless Networks
Abstract
Along with the rapid development and deployment of real-time wireless network (RTWN) technologies in a wide range of applications, effective packet scheduling algorithms have been playing a critical role in RTWNs for achieving desired Quality of Service (QoS) for real-time sensing and control, especially in the presence of unexpected disturbances. Most existing solutions in the literature focus either on static or dynamic schedule construction to meet the desired QoS requirements, but have a common assumption that all wireless links are reliable. Although this assumption simplifies the algorithm design and analysis, it is not realistic in real-life settings. To address this drawback, this paper introduces a novel reliable dynamic packet scheduling framework, called RD-PaS. RD-PaS can not only construct static schedules to meet both the timing and reliability requirements of end-to-end packet transmissions in RTWNs for a given periodic network traffic pattern, but also construct new schedules rapidly to handle abruptly increased network traffic induced by unexpected disturbances while minimizing the impact on existing network flows. The functional correctness of the RD-PaS framework has been validated through its implementation and deployment on a real-life RTWN testbed. Extensive simulation-based experiments have also been performed to evaluate the effectiveness of RD-PaS, especially in large-scale network settings.
Cite as
Tao Gong, Tianyu Zhang, Xiaobo Sharon Hu, Qingxu Deng, Michael Lemmon, and Song Han. Reliable Dynamic Packet Scheduling over Lossy Real-Time Wireless Networks. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 11:1-11:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{gong_et_al:LIPIcs.ECRTS.2019.11,
author = {Gong, Tao and Zhang, Tianyu and Hu, Xiaobo Sharon and Deng, Qingxu and Lemmon, Michael and Han, Song},
title = {{Reliable Dynamic Packet Scheduling over Lossy Real-Time Wireless Networks}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {11:1--11:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.11},
URN = {urn:nbn:de:0030-drops-107482},
doi = {10.4230/LIPIcs.ECRTS.2019.11},
annote = {Keywords: Real-time wireless networks, lossy links, dynamic packet scheduling, reliability}
}
Document
Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems
Abstract
Composable many-core systems enable the independent development and analysis of applications which will be executed on a shared platform where the mix of concurrently executed applications may change dynamically at run time. For each individual application, an off-line DSE is performed to compute several mapping alternatives on the platform, offering Pareto-optimal trade-offs in terms of real-time guarantees, resource usage, etc. At run time, one mapping is then chosen to launch the application on demand. In this context, to enable an independent analysis of each individual application at design time, so-called inter-application isolation schemes are applied which specify temporal/spatial isolation policies between applications. State-of-the-art composable many-core systems are developed based on a fixed isolation scheme that is exclusively applied to every resource in every mapping of every application and use a timing analysis tailored to that isolation scheme to derive timing guarantees for each mapping. A fixed isolation scheme, however, heavily restricts the explored space of solutions and can, therefore, lead to suboptimality. Lifting this restriction necessitates a timing analysis that is applicable to mappings with an arbitrary mix of isolation schemes on different resources. To address this issue, in this paper, we (a) present an isolation-aware timing analysis that - unlike existing analyses - can handle multiple isolation schemes in combination within one mapping and delivers safe yet tight timing bounds by identifying and excluding interference scenarios that can never happen under the given combination of isolation schemes. Based on the timing analysis, we (b) present a DSE which explores the choices of isolation scheme per resource within each mapping and uses the proposed timing analysis for timing verification. Experimental results demonstrate that, for a variety of real-time applications and many-core platforms, the proposed approach achieves an improvement of up to 67% in the quality of delivered mappings compared to approaches based on a fixed isolation scheme.
Cite as
Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, and Jürgen Teich. Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 12:1-12:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{pourmohseni_et_al:LIPIcs.ECRTS.2019.12,
author = {Pourmohseni, Behnaz and Smirnov, Fedor and Wildermann, Stefan and Teich, J\"{u}rgen},
title = {{Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {12:1--12:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.12},
URN = {urn:nbn:de:0030-drops-107491},
doi = {10.4230/LIPIcs.ECRTS.2019.12},
annote = {Keywords: Many-core systems, timing analysis, design space exploration (DSE), isolation scheme, predictability, composability}
}
Document
GEDF Tardiness: Open Problems Involving Uniform Multiprocessors and Affinity Masks Resolved
Abstract
Prior work has shown that the global earliest-deadline-first (GEDF) scheduler is soft real-time (SRT)-optimal for sporadic task systems in a variety of contexts, meaning that bounded deadline tardiness can be guaranteed under it for any task system that does not cause platform overutilization. However, one particularly compelling context has remained elusive: multiprocessor platforms in which tasks have affinity masks that determine the processors where they may execute. Actual GEDF implementations, such as the SCHED_DEADLINE class in Linux, have dealt with this unresolved question by foregoing SRT guarantees once affinity masks are set. This unresolved question, as it pertains to SCHED_DEADLINE, was included by Peter Zijlstra in a list of important open problems affecting Linux in his keynote talk at ECRTS 2017. In this paper, this question is resolved along with another open problem that at first blush seems unrelated but actually is. Specifically, both problems are closed by establishing two results. First, a proof strategy used previously to establish GEDF tardiness bounds that are exponential in size on heterogeneous uniform multiprocessors is generalized to show that polynomial bounds exist on a wider class of platforms. Second, both uniform multiprocessors and identical multiprocessors with affinities are shown to be within this class. These results yield the first polynomial GEDF tardiness bounds for the uniform case and the first such bounds of any kind for the identical-with-affinities case.
Cite as
Stephen Tang, Sergey Voronov, and James H. Anderson. GEDF Tardiness: Open Problems Involving Uniform Multiprocessors and Affinity Masks Resolved. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 13:1-13:21, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{tang_et_al:LIPIcs.ECRTS.2019.13,
author = {Tang, Stephen and Voronov, Sergey and Anderson, James H.},
title = {{GEDF Tardiness: Open Problems Involving Uniform Multiprocessors and Affinity Masks Resolved}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {13:1--13:21},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.13},
URN = {urn:nbn:de:0030-drops-107504},
doi = {10.4230/LIPIcs.ECRTS.2019.13},
annote = {Keywords: scheduling theory, multicore, processor affinity masks, GEDF, uniform multiprocessors}
}
Document
Dual Priority Scheduling is Not Optimal
Abstract
In dual priority scheduling, periodic tasks are executed in a fixed-priority manner, but each job has two phases with different priorities. The second phase is entered after a fixed amount of time has passed since the release of the job, at which point the job changes its priority. Dual priority scheduling was introduced by Burns and Wellings in 1993 and was shown to successfully schedule many task sets that are not schedulable with ordinary (single) fixed-priority scheduling. Burns and Wellings conjectured that dual priority scheduling is an optimal scheduling algorithm for synchronous periodic tasks with implicit deadlines on preemptive uniprocessors. We demonstrate the falsity of this conjecture, as well as of some related conjectures that have since been stated. This is achieved by means of computer-verified counterexamples.
Cite as
Pontus Ekberg. Dual Priority Scheduling is Not Optimal. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 14:1-14:9, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{ekberg:LIPIcs.ECRTS.2019.14,
author = {Ekberg, Pontus},
title = {{Dual Priority Scheduling is Not Optimal}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {14:1--14:9},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.14},
URN = {urn:nbn:de:0030-drops-107519},
doi = {10.4230/LIPIcs.ECRTS.2019.14},
annote = {Keywords: Scheduling, real time systems, dual priority}
}
Document
NPM-BUNDLE: Non-Preemptive Multitask Scheduling for Jobs with BUNDLE-Based Thread-Level Scheduling
Abstract
The BUNDLE and BUNDLEP scheduling algorithms are cache-cognizant thread-level scheduling algorithms and associated worst case execution time and cache overhead (WCETO) techniques for hard real-time multi-threaded tasks. The BUNDLE-based approaches utilize the inter-thread cache benefit to reduce WCETO values for jobs. Currently, the BUNDLE-based approaches are limited to scheduling a single task. This work aims to expand the applicability of BUNDLE-based scheduling to multiple task multi-threaded task sets.
BUNDLE-based scheduling leverages knowledge of potential cache conflicts to selectively preempt one thread in favor of another from the same job. This thread-level preemption is a requirement for the run-time behavior and WCETO calculation to receive the benefit of BUNDLE-based approaches. This work proposes scheduling BUNDLE-based jobs non-preemptively according to the earliest deadline first (EDF) policy. Jobs are forbidden from preempting one another, while threads within a job are allowed to preempt other threads.
An accompanying schedulability test is provided, named Threads Per Job (TPJ). TPJ is a novel schedulability test, input is a task set specification which may be transformed (under certain restrictions); dividing threads among tasks in an effort to find a feasible task set. Enhanced by the flexibility to transform task sets and taking advantage of the inter-thread cache benefit, the evaluation shows TPJ scheduling task sets fully preemptive EDF cannot.
Cite as
Corey Tessler and Nathan Fisher. NPM-BUNDLE: Non-Preemptive Multitask Scheduling for Jobs with BUNDLE-Based Thread-Level Scheduling. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 15:1-15:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{tessler_et_al:LIPIcs.ECRTS.2019.15,
author = {Tessler, Corey and Fisher, Nathan},
title = {{NPM-BUNDLE: Non-Preemptive Multitask Scheduling for Jobs with BUNDLE-Based Thread-Level Scheduling}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {15:1--15:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.15},
URN = {urn:nbn:de:0030-drops-107521},
doi = {10.4230/LIPIcs.ECRTS.2019.15},
annote = {Keywords: Scheduling algorithms, Cache Memory, Multi-threading, Static Analysis}
}
Document
Scheduling Self-Suspending Tasks: New and Old Results
Abstract
In computing systems, a job may suspend itself (before it finishes its execution) when it has to wait for certain results from other (usually external) activities. For real-time systems, such self-suspension behavior has been shown to induce performance degradation. Hence, the researchers in the real-time systems community have devoted themselves to the design and analysis of scheduling algorithms that can alleviate the performance penalty due to self-suspension behavior. As self-suspension and delegation of parts of a job to non-bottleneck resources is pretty natural in many applications, researchers in the operations research (OR) community have also explored scheduling algorithms for systems with such suspension behavior, called the master-slave problem in the OR community.
This paper first reviews the results for the master-slave problem in the OR literature and explains their impact on several long-standing problems for scheduling self-suspending real-time tasks. For frame-based periodic real-time tasks, in which the periods of all tasks are identical and all jobs related to one frame are released synchronously, we explore different approximation metrics with respect to resource augmentation factors under different scenarios for both uniprocessor and multiprocessor systems, and demonstrate that different approximation metrics can create different levels of difficulty for the approximation. Our experimental results show that such more carefully designed schedules can significantly outperform the state-of-the-art.
Cite as
Jian-Jia Chen, Tobias Hahn, Ruben Hoeksma, Nicole Megow, and Georg von der Brüggen. Scheduling Self-Suspending Tasks: New and Old Results. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 16:1-16:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{chen_et_al:LIPIcs.ECRTS.2019.16,
author = {Chen, Jian-Jia and Hahn, Tobias and Hoeksma, Ruben and Megow, Nicole and von der Br\"{u}ggen, Georg},
title = {{Scheduling Self-Suspending Tasks: New and Old Results}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {16:1--16:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.16},
URN = {urn:nbn:de:0030-drops-107532},
doi = {10.4230/LIPIcs.ECRTS.2019.16},
annote = {Keywords: Self-suspension, master-slave problem, computational complexity, speedup factors}
}
Document
Impact of DM-LRU on WCET: A Static Analysis Approach
Abstract
Cache memories in modern embedded processors are known to improve average memory access performance. Unfortunately, they are also known to represent a major source of unpredictability for hard real-time workload. One of the main limitations of typical caches is that content selection and replacement is entirely performed in hardware. As such, it is hard to control the cache behavior in software to favor caching of blocks that are known to have an impact on an application’s worst-case execution time (WCET).
In this paper, we consider a cache replacement policy, namely DM-LRU, that allows system designers to prioritize caching of memory blocks that are known to have an important impact on an application’s WCET. Considering a single-core, single-level cache hierarchy, we describe an abstract interpretation-based timing analysis for DM-LRU. We implement the proposed analysis in a self-contained toolkit and study its qualitative properties on a set of representative benchmarks. Apart from being useful to compute the WCET when DM-LRU or similar policies are used, the proposed analysis can allow designers to perform WCET impact-aware selection of content to be retained in cache.
Cite as
Renato Mancuso, Heechul Yun, and Isabelle Puaut. Impact of DM-LRU on WCET: A Static Analysis Approach. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 17:1-17:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{mancuso_et_al:LIPIcs.ECRTS.2019.17,
author = {Mancuso, Renato and Yun, Heechul and Puaut, Isabelle},
title = {{Impact of DM-LRU on WCET: A Static Analysis Approach}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {17:1--17:25},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.17},
URN = {urn:nbn:de:0030-drops-107546},
doi = {10.4230/LIPIcs.ECRTS.2019.17},
annote = {Keywords: real-time, static cache analysis, abstract interpretation, LRU, deterministic memory, static cache locking, dynamic cache locking, cache profiling, WCET analysis}
}
Document
Modeling Cache Coherence to Expose Interference
Abstract
To facilitate programming, most multi-core processors feature automated mechanisms maintaining coherence between each core’s cache. These mechanisms introduce interference, that is, delays caused by concurrent access to a shared resource. This type of interference is hard to predict, leading to the mechanisms being shunned by real-time system designers, at the cost of potential benefits in both running time and system complexity.
We believe that formal methods can provide the means to ensure that the effects of this interference are properly exposed and mitigated. Consequently, this paper proposes a nascent framework relying on timed automata to model and analyze the interference caused by cache coherence.
Cite as
Nathanaël Sensfelder, Julien Brunel, and Claire Pagetti. Modeling Cache Coherence to Expose Interference. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 18:1-18:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{sensfelder_et_al:LIPIcs.ECRTS.2019.18,
author = {Sensfelder, Nathana\"{e}l and Brunel, Julien and Pagetti, Claire},
title = {{Modeling Cache Coherence to Expose Interference}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {18:1--18:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.18},
URN = {urn:nbn:de:0030-drops-107553},
doi = {10.4230/LIPIcs.ECRTS.2019.18},
annote = {Keywords: Real-time systems, multi-core processor, cache coherence, formal methods}
}
Document
Arbitration-Induced Preemption Delays
Abstract
The interactions among concurrent tasks pose a challenge in the design of real-time multi-core systems, where blocking delays that tasks may experience while accessing shared memory have to be taken into consideration. Various memory arbitration schemes have been devised that address these issues, by providing trade-offs between predictability, average-case performance, and analyzability. Time-Division Multiplexing (TDM) is a well-known arbitration scheme due to its simplicity and analyzability. However, it suffers from low resource utilization due to its non-work-conserving nature. We proposed in our recent work dynamic schemes based on TDM, showing work-conserving behavior in practice, while retaining the guarantees of TDM. These approaches have only been evaluated in a restricted setting. Their applicability in a preemptive setting appears problematic, since they may induce long memory blocking times depending on execution history. These blocking delays may induce significant jitter and consequently increase the tasks' response times.
This work explores means to manage and, finally, bound these blocking delays. Three different schemes are explored and compared with regard to their analyzability, impact on response-time analysis, implementation complexity, and runtime behavior. Experiments show that the various approaches behave virtually identically at runtime. This allows to retain the approach combining low implementation complexity with analyzability.
Cite as
Farouk Hebbache, Florian Brandner, Mathieu Jan, and Laurent Pautet. Arbitration-Induced Preemption Delays. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 19:1-19:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{hebbache_et_al:LIPIcs.ECRTS.2019.19,
author = {Hebbache, Farouk and Brandner, Florian and Jan, Mathieu and Pautet, Laurent},
title = {{Arbitration-Induced Preemption Delays}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {19:1--19:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.19},
URN = {urn:nbn:de:0030-drops-107564},
doi = {10.4230/LIPIcs.ECRTS.2019.19},
annote = {Keywords: Dynamic Time-Division Multiplexing, Predictable Computing, Multi-Criticality, Preemption}
}
Document
Fast and Effective Multiframe-Task Parameter Assignment Via Concave Approximations of Demand
Abstract
Task parameters in traditional models, e.g., the generalized multiframe (GMF) model, are fixed after task specification time. When tasks whose parameters can be assigned within a range, such as the frame parameters in self-suspending tasks and end-to-end tasks, the optimal offline assignment towards schedulability of such parameters becomes important. The GMF-PA (GMF with parameter adaptation) model proposed in recent work allows frame parameters to be flexibly chosen (offline) in arbitrary-deadline systems. Based on the GMF-PA model, a mixed-integer linear programming (MILP)-based schedulability test was previously given under EDF scheduling for a given assignment of frame parameters in uniprocessor systems. Due to the NP-hardness of the MILP, we present a pseudo-polynomial linear programming (LP)-based heuristic algorithm guided by a concave approximation algorithm to achieve a feasible parameter assignment at a fraction of the time overhead of the MILP-based approach. The concave programming approximation algorithm closely approximates the MILP algorithm, and we prove its speed-up factor is (1+delta)^2 where delta > 0 can be arbitrarily small, with respect to the exact schedulability test of GMF-PA tasks under EDF. Extensive experiments involving self-suspending tasks (an application of the GMF-PA model) reveal that the schedulability ratio is significantly improved compared to other previously proposed polynomial-time approaches in medium and moderately highly loaded systems.
Cite as
Bo Peng, Nathan Fisher, and Thidapat Chantem. Fast and Effective Multiframe-Task Parameter Assignment Via Concave Approximations of Demand. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 20:1-20:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{peng_et_al:LIPIcs.ECRTS.2019.20,
author = {Peng, Bo and Fisher, Nathan and Chantem, Thidapat},
title = {{Fast and Effective Multiframe-Task Parameter Assignment Via Concave Approximations of Demand}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {20:1--20:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.20},
URN = {urn:nbn:de:0030-drops-107578},
doi = {10.4230/LIPIcs.ECRTS.2019.20},
annote = {Keywords: generalized multiframe task model (GMF), generalized multiframe task model with parameter adaptation (GMF-PA), self-suspending tasks, uniprocessor scheduling, mixed-integer linear programming, concave approximation, linear programming}
}
Document
Response-Time Analysis of Limited-Preemptive Parallel DAG Tasks Under Global Scheduling
Abstract
Most recurrent real-time applications can be modeled as a set of sequential code segments (or blocks) that must be (repeatedly) executed in a specific order. This paper provides a schedulability analysis for such systems modeled as a set of parallel DAG tasks executed under any limited-preemptive global job-level fixed priority scheduling policy. More precisely, we derive response-time bounds for a set of jobs subject to precedence constraints, release jitter, and execution-time uncertainty, which enables support for a wide variety of parallel, limited-preemptive execution models (e.g., periodic DAG tasks, transactional tasks, generalized multi-frame tasks, etc.). Our analysis explores the space of all possible schedules using a powerful new state abstraction and state-pruning technique. An empirical evaluation shows the analysis to identify between 10 to 90 percentage points more schedulable task sets than the state-of-the-art schedulability test for limited-preemptive sporadic DAG tasks. It scales to systems of up to 64 cores with 20 DAG tasks. Moreover, while our analysis is almost as accurate as the state-of-the-art exact schedulability test based on model checking (for sequential non-preemptive tasks), it is three orders of magnitude faster and hence capable of analyzing task sets with more than 60 tasks on 8 cores in a few seconds.
Cite as
Mitra Nasri, Geoffrey Nelissen, and Björn B. Brandenburg. Response-Time Analysis of Limited-Preemptive Parallel DAG Tasks Under Global Scheduling. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 21:1-21:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{nasri_et_al:LIPIcs.ECRTS.2019.21,
author = {Nasri, Mitra and Nelissen, Geoffrey and Brandenburg, Bj\"{o}rn B.},
title = {{Response-Time Analysis of Limited-Preemptive Parallel DAG Tasks Under Global Scheduling}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {21:1--21:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.21},
URN = {urn:nbn:de:0030-drops-107587},
doi = {10.4230/LIPIcs.ECRTS.2019.21},
annote = {Keywords: parallel DAG tasks, global multiprocessor scheduling, schedulability analysis, non-preemptive jobs, precedence constraints, worst-case response time, OpenMP}
}
Document
Novel Methodologies for Predictable CPU-To-GPU Command Offloading
Abstract
There is an increasing industrial and academic interest towards a more predictable characterization of real-time tasks on high-performance heterogeneous embedded platforms, where a host system offloads parallel workloads to an integrated accelerator, such as General Purpose-Graphic Processing Units (GP-GPUs). In this paper, we analyze an important aspect that has not yet been considered in the real-time literature, and that may significantly affect real-time performance if not properly treated, i.e., the time spent by the CPU for submitting GP-GPU operations. We will show that the impact of CPU-to-GPU kernel submissions may be indeed relevant for typical real-time workloads, and that it should be properly factored in when deriving an integrated schedulability analysis for the considered platforms.
This is the case when an application is composed of many small and consecutive GPU compute/copy operations. While existing techniques mitigate this issue by batching kernel calls into a reduced number of persistent kernel invocations, in this work we present and evaluate three other approaches that are made possible by recently released versions of the NVIDIA CUDA GP-GPU API, and by Vulkan, a novel open standard GPU API that allows an improved control of GPU command submissions. We will show that this added control may significantly improve the application performance and predictability due to a substantial reduction in CPU-to-GPU driver interactions, making Vulkan an interesting candidate for becoming the state-of-the-art API for heterogeneous Real-Time systems.
Our findings are evaluated on a latest generation NVIDIA Jetson AGX Xavier embedded board, executing typical workloads involving Deep Neural Networks of parameterized complexity.
Cite as
Roberto Cavicchioli, Nicola Capodieci, Marco Solieri, and Marko Bertogna. Novel Methodologies for Predictable CPU-To-GPU Command Offloading. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 22:1-22:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{cavicchioli_et_al:LIPIcs.ECRTS.2019.22,
author = {Cavicchioli, Roberto and Capodieci, Nicola and Solieri, Marco and Bertogna, Marko},
title = {{Novel Methodologies for Predictable CPU-To-GPU Command Offloading}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {22:1--22:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.22},
URN = {urn:nbn:de:0030-drops-107595},
doi = {10.4230/LIPIcs.ECRTS.2019.22},
annote = {Keywords: Heterogeneous systems, GPU, CUDA, Vulkan}
}
Document
Generating and Exploiting Deep Learning Variants to Increase Heterogeneous Resource Utilization in the NVIDIA Xavier
Abstract
Deep learning-based solutions and, in particular, deep neural networks (DNNs) are at the heart of several functionalities in critical-real time embedded systems (CRTES) from vision-based perception (object detection and tracking) systems to trajectory planning. As a result, several DNN instances simultaneously run at any time on the same computing platform. However, while modern GPUs offer a variety of computing elements (e.g. CPUs, GPUs, and specific accelerators) in which those DNN tasks can be executed depending on their computational requirements and temporal constraints, current DNNs are mainly programmed to exploit one of them, namely, regular cores in the GPU. This creates resource imbalance and under-utilization of GPU resources when executing several DNN instances, causing an increase in DNN tasks' execution time requirements. In this paper, (a) we develop different variants (implementations) of well-known DNN libraries used in the Apollo Autonomous Driving (AD) software for each of the computing elements of the latest NVIDIA Xavier SoC. Each variant can be configured to balance resource requirements and performance: the regular CPU core implementation that can run on 2, 4, and 6 cores; the GPU regular and Tensor core variants that can run in 4 or 8 GPU’s Streaming Multiprocessors (SM); and 1 or 2 NVIDIA’s Deep Learning Accelerators (NVDLA); (b) we show that each particular variant/configuration offers a different resource utilization/performance point; finally, (c) we show how those heterogeneous computing elements can be exploited by a static scheduler to sustain the execution of multiple and diverse DNN variants on the same platform.
Cite as
Roger Pujol, Hamid Tabani, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, and Francisco J. Cazorla. Generating and Exploiting Deep Learning Variants to Increase Heterogeneous Resource Utilization in the NVIDIA Xavier. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 23:1-23:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{pujol_et_al:LIPIcs.ECRTS.2019.23,
author = {Pujol, Roger and Tabani, Hamid and Kosmidis, Leonidas and Mezzetti, Enrico and Abella, Jaume and Cazorla, Francisco J.},
title = {{Generating and Exploiting Deep Learning Variants to Increase Heterogeneous Resource Utilization in the NVIDIA Xavier}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {23:1--23:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.23},
URN = {urn:nbn:de:0030-drops-107608},
doi = {10.4230/LIPIcs.ECRTS.2019.23},
annote = {Keywords: Deep Neural Network (DNN), GPU, Heterogenous Resources}
}
Document
A Bandwidth Reservation Mechanism for AXI-Based Hardware Accelerators on FPGAs
Abstract
Hardware platforms for real-time embedded systems are evolving towards heterogeneous architectures comprising different types of processing cores and dedicated hardware accelerators, which can be implemented on silicon or dynamically deployed on FPGA fabric. Such accelerators typically access a shared memory to exchange a significant amount of data with other processing elements. Existing COTS solutions focus on maximizing the overall throughput of the system, rather than guaranteeing the timing constraints of individual hardware accelerators. This paper presents the AXI budgeting unit (ABU), a hardware-based solution to implement a bandwidth reservation mechanism on top of the AMBA AXI standard infrastructure for hardware accelerators deployed on FPGAs. An accurate and tractable model, as well as the corresponding analysis, are also proposed to bound the response time of hardware accelerators in the presence of ABUs, in order to verify whether they can complete before their deadlines. Finally, a set of experiments are reported to evaluate the proposed approach on a state-of-the-art platform, namely the Zynq-7020 by Xilinx. The resource consumption of the ABU has been quantified to be less than 1% of the total FPGA resources of the Zynq-7020.
Cite as
Marco Pagani, Enrico Rossi, Alessandro Biondi, Mauro Marinoni, Giuseppe Lipari, and Giorgio Buttazzo. A Bandwidth Reservation Mechanism for AXI-Based Hardware Accelerators on FPGAs. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 24:1-24:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{pagani_et_al:LIPIcs.ECRTS.2019.24,
author = {Pagani, Marco and Rossi, Enrico and Biondi, Alessandro and Marinoni, Mauro and Lipari, Giuseppe and Buttazzo, Giorgio},
title = {{A Bandwidth Reservation Mechanism for AXI-Based Hardware Accelerators on FPGAs}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {24:1--24:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.24},
URN = {urn:nbn:de:0030-drops-107611},
doi = {10.4230/LIPIcs.ECRTS.2019.24},
annote = {Keywords: AXI Bus, Bandwidth Reservation, Hardware Acceleration, FPGA}
}
Document
Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures
Abstract
Multi-core systems using ScratchPad Memories (SPMs) are attractive architectures for executing time-critical embedded applications, because they provide both predictability and performance. In this paper, we propose a scheduling technique that jointly selects SPM contents off-line, in such a way that the cost of SPM loading/unloading is hidden. Communications are fragmented to augment hiding possibilities. Experimental results show the effectiveness of the proposed technique on streaming applications and synthetic task-graphs. The overlapping of communications with computations allows the length of generated schedules to be reduced by 4% on average on streaming applications, with a maximum of 16%, and by 8% on average for synthetic task graphs. We further show on a case study that generated schedules can be implemented with low overhead on a predictable multi-core architecture (Kalray MPPA).
Cite as
Benjamin Rouxel, Stefanos Skalistis, Steven Derrien, and Isabelle Puaut. Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 25:1-25:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{rouxel_et_al:LIPIcs.ECRTS.2019.25,
author = {Rouxel, Benjamin and Skalistis, Stefanos and Derrien, Steven and Puaut, Isabelle},
title = {{Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {25:1--25:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.25},
URN = {urn:nbn:de:0030-drops-107626},
doi = {10.4230/LIPIcs.ECRTS.2019.25},
annote = {Keywords: Real-time Systems, Contention-Free Scheduling, SPM multi-core architecture}
}
Document
Slot-Based Transmission Protocol for Real-Time NoCs - SBT-NoC
Abstract
Network on Chip (NoC) interconnects are some of the most challenging-to-analyse components of multiprocessor platforms. This is primarily due to the following two reasons: (i) NoCs contain numerous shared resources (e.g. routers, links), and (ii) the network traffic often concurrently traverses multiple of those resources. Consequently, complex contention scenarios among traffic flows might occur, some of the important implications being significant performance limitations, and difficulties when performing the real-time analysis. In this work, we propose a slot-based transmission protocol for NoCs (called SBT-NoC), and an accompanying analysis method for deriving worst-case traffic latencies. The cornerstone of SBT-NoC is a contention-less slot-based transmission, arbitrated via a protocol running on a dedicated network medium. The main advantage of SBT-NoC is that, while not requiring any sophisticated hardware support (e.g. virtual channels, a flit-level arbitration), it makes NoCs amenable to real-time analysis and guarantees bounded low latencies of high-priority time-critical flows, which is a sine qua non for the inclusion of NoCs, and multiprocessors in general, in the real-time domain. The experimental evaluation, including both synthetic workloads and a use-case of an autonomous driving vehicle application, reveals that SBT-NoC offers a plethora of configuration opportunities, which makes it applicable to a wide range of diverse traffic workloads.
Cite as
Borislav Nikolić, Robin Hofmann, and Rolf Ernst. Slot-Based Transmission Protocol for Real-Time NoCs - SBT-NoC. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 26:1-26:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{nikolic_et_al:LIPIcs.ECRTS.2019.26,
author = {Nikoli\'{c}, Borislav and Hofmann, Robin and Ernst, Rolf},
title = {{Slot-Based Transmission Protocol for Real-Time NoCs - SBT-NoC}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {26:1--26:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.26},
URN = {urn:nbn:de:0030-drops-107633},
doi = {10.4230/LIPIcs.ECRTS.2019.26},
annote = {Keywords: Real-Time Systems, Embedded Systems, Network-on-Chip, Protocols}
}
Document
Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms
Abstract
Multiprocessor Systems-on-Chip (MPSoC) integrating hard processing cores with programmable logic (PL) are becoming increasingly common. While these platforms have been originally designed for high performance computing applications, their rich feature set can be exploited to efficiently implement mixed criticality domains serving both critical hard real-time tasks, as well as soft real-time tasks.
In this paper, we take a deep look at commercially available heterogeneous MPSoCs that incorporate PL and a multicore processor. We show how one can tailor these processors to support a mixed criticality system, where cores are strictly isolated to avoid contention on shared resources such as Last-Level Cache (LLC) and main memory. In order to avoid conflicts in last-level cache, we propose the use of cache coloring, implemented in the Jailhouse hypervisor. In addition, we employ ScratchPad Memory (SPM) inside the PL to support a multi-phase execution model for real-time tasks that avoids conflicts in shared memory. We provide a full-stack, working implementation on a latest-generation MPSoC platform, and show results based on both a set of data intensive tasks, as well as a case study based on an image processing benchmark application.
Cite as
Giovani Gracioli, Rohan Tabish, Renato Mancuso, Reza Mirosanlou, Rodolfo Pellizzoni, and Marco Caccamo. Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 27:1-27:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)
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@InProceedings{gracioli_et_al:LIPIcs.ECRTS.2019.27,
author = {Gracioli, Giovani and Tabish, Rohan and Mancuso, Renato and Mirosanlou, Reza and Pellizzoni, Rodolfo and Caccamo, Marco},
title = {{Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms}},
booktitle = {31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
pages = {27:1--27:25},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-110-8},
ISSN = {1868-8969},
year = {2019},
volume = {133},
editor = {Quinton, Sophie},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops-dev.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.27},
URN = {urn:nbn:de:0030-drops-107645},
doi = {10.4230/LIPIcs.ECRTS.2019.27},
annote = {Keywords: Mixed-criticality systems, SoC Heterogeneous platforms, FPGA, real-time computing}
}