LZI - Schloss Dagstuhl - Talks + Materials of Seminar 06141

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Seminar 06141
Dynamically Reconfigurable Architectures

P. M. Athanas (Virginia Polytechnic Institute, US), J. Becker (Universität Karlsruhe, DE), G. Brebner (Xilinx - San José, US), J. Teich (Universität Erlangen, DE)

Seminar Wide Materials

Final Workshop Program

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Wael Adi , TU Braunschweig

IP Cores Protection in FPGA Environment, Cryptographic Identification Primitives

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Peter M. Athanas , Virginia Polytechnic Institute

The (empty?) Promise of FPGA Supercomputing

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DROPS-Submission:

Jürgen Becker , Universität Karlsruhe

Mladen Berekovic , Delft University of Technology

The ADRES coarse-grained reconfigurable Array Processor

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Neil W. Bergmann , The University of Queensland

HW/SW Codesign for Reconfigurable System-on-Chip using a Process Model

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Christophe Bobda , TU Kaiserslautern

Adaptive On-Chip Multiprocessing

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Gordon Brebner , Xilinx - San José

Dynamically Adaptable Behaviours (?)

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Rainer Buchty , Universität Karlsruhe

Reconfigurable Architectures and Instruction Sets: Programmability, Code Generation, and Program Execution

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DROPS-Submission:

Oliver Diessel , Univ. of New South Wales

Enabling RTR for industry

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Florian Dittmann , Universität Paderborn

Reconfiguration Time Aware Processing on FPGAs

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DROPS-Submission:

Dietmar Fey , Universität Jena

Technological Aspects for 3D FPGAs architectures with optoelectronic interconnects

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Manfred Glesner , TU Darmstadt

Diana Göhringer , Universität Erlangen

Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine

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DROPS-Submission:

Reiner Hartenstein , TU Kaiserslautern

Reconfigurable Supercomputing: What are the Problems? What are the Solutions?

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Sven Heithecker , TU Braunschweig

FlexFilm - an Image Processor for Digital Film Processing

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DROPS-Submission:

Andreas Herkersdorf , TU München

Reconfigurable Functionality vs. Reconfigurable Interconnects

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DROPS-Submission:

Christian Hochberger , TU Dresden

AMIDAR: A new Modell for Adaptive Processors

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Michael Hübner , Universität Karlsruhe

Physical 2D Morphware and Power Reduction Methods for Everyone

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Physical 2D Morphware and Power Reduction Methods for Everyone

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DROPS-Submission:

Wolfgang Karl , Universität Karlsruhe

David Kearney , Univ. of South Australia

Managing power amongst a group of networked embedded fpgas using dynamic reconfiguration and task migration

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Bernd Klauer , Helmut-Schmidt-Universität - Hamburg

Superscalar Technology for Reconfigurable Processors

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Andreas Koch , TU Darmstadt

Back-End Issues in Hardware/Software-Compilation

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Shannon Koh , Univ. of New South Wales

Enabling RTR for industry

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Jean-Christophe Le Lann , University of Brest

Philip Leong , Imperial College London

Floating Point FPGAs

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Amilcar Lucas , TU Braunschweig

FlexFilm - an Image Processor for Digital Film Processing

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Mateusz Majer , Universität Erlangen

Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine

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Douglas Maskell , Nanyang Technological University - Singapore

Martin Middendorf , Universität Leipzig

Multi-level Reconfigurable Architectures - The Switch Model

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Vincent J. Mooney , Georgia Institute of Technology

Low Level Compiler for XMonarch

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Design of a Hardware/Software RTOS for FPGAs with Processors

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Center for Research on Embedded Systems and Technology

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Hardware/Software Codesign of a Real-Time Operating System

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Katarina Paulsson , Universität Karlsruhe

Thilo Pionteck , Universität Lübeck

DynaCORE: An Adaptive System-on-Chip Architecture for Deep Packet Processing in Network Applications

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Marco Platzner , Universität Paderborn

Mapping Periodic Realtime Tasks to Reconfigurable Hardware

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Wolfgang Rosenstiel , Universität Tübingen

Dynamically Reconfigurable Processor-Like Architectures

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Hartmut Schmeck , Universität Karlsruhe

Implications of Organic Computing for Reconfigurable Computing

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Sunil Kumar Shukla , Universität Karlsruhe

QUKU: A Coarse Grained Paradigm for FPGAs

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DROPS-Submission:

Gerard Smit , University of Twente

Efficient Reconfigurable Architectures for streaming DSP applications

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Efficient architectures for streaming applications

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DROPS-Submission:

John Snowdon , Heriot-Watt University Edinburgh

Optoelectronic methods to beat Moore's Law

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Free-Space Optical Interconnected Topologies for Embedded Compute Applications with Experimental Validation using Rapid Prototyping techniques

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Walter Stechele , TU München

Dynamically Reconfigurable Systems-on-Chip

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DROPS-Submission:

Jürgen Teich , Universität Erlangen

Libraries for Reconfigurable Computing

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ReCoLib - Libraries for Reconfigurable Computing

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Jozsef Vasarhelyi , University of Miskolc

Mojette Transform implementation on reconfigurable hardware

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DROPS-Submission:

Stamatis Vassiliadis , Delft University of Technology

PISC: Polymorphic Instruction Set Computers

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Klaus Waldschmidt , Universität Frankfurt

Reliability-Aware Power Management of Multi-CoreProcessors in Modern Reconfigurable System-On-Chips

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DROPS-Submission:

Norbert Wehn , TU Kaiserslautern

A Reconfigurable Outer Modem Platform for Future Communications Systems

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DROPS-Submission:

Roger Woods , Queen's University of Belfast

Implementing High Performance DSP Systems on Heterogeneous Programmable Platforms

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Peter Zipf , TU Darmstadt

Towards an Automated Design of Application-specific Reconfigurable Logic

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DROPS-Submission:

Jan van der Veen , TU Braunschweig

Libraries for Reconfigurable Computing

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Seminar 06141 Dynamically Reconfigurable Architectures

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Seminar 06141
Dynamically Reconfigurable Architectures