We present new processor instructions that can accelerate AES and AES-GCM. Four instructions accelerate round encryption and decryp-tion whereas a fifth instruction accelerates the computation of the carry-less product of 2 64-bit operands.  Our instructions not only offer high performance implementation of cryptographic transformations but also mitigate software side channel attacks. We present the instruction specification as well as a novel technique for implementing the GCM mode for AES [17].  Our technique is based on a fast reduction method that eliminates the need for putting field specific-reduction logic into the implementation of a processor instruction.