We demonstrate how hardware fine-grained memory protection can be
used in support of transactional memory systems: first showing
how a software transactional memory system (STM) can be made
strongly atomic by using memory protection on transactionally-held
state, then showing how such a strongly-atomic STM can be used
with a bounded hardware TM system to build a hybrid TM system
in which zero-overhead hardware transactions may safely run concurrently
with potentially-conflicting software transactions.

In addition, I quickly survey 5 other topics: 1) that speculative compiler 
optimization is a second killer application for TM/SLE hardware, 2) the 
keys for good hybrid performance are: good hardware contention management
and hardware feedback on the reason for an abort, 3) how important is
concurrency within a transaction (I don't think hardware can help this case),
4) that single-thread performance is important for scalability because how 
fast each thread commits determines the level of contention where there are 
conflicts, and 5) a question for the community as to what the desired performance
profile (perf. vs. transaction size); is it more important to have maximal 
performance for small and medium transactions, or is it more important to 
have smooth performance of transactions (no discontinuities) as memory 
footprints increase in size?