Affine control loops (ACLs) constitute an important class of compute
and data intensive programs. Domain specific SIMD architectures are
an attractive target for direct hardware implementation of such programs.
This compilation requires, in the most general case, interconnections
which (i) are affine functions of the PEs and (ii) change dynamically
with program execution. We propose a reconfigurable, on-chip, interconnection
network, called GRAIL, that supports such temporally changing affine
interconnections through constant time reconfiguration. It is generic
in the sense that the same fabric can be (re)used to support any affine
communication pattern. The GRAIL may be viewed as a non-blocking circuit-switched
multistage interconnection network that has an attractive cost-connectivity
tradeoff vis-a-vis traditional networks. We describe the properties
of interconnections realized by a GRAIL, and show how the switch settings
as well as the dynamic reconfigurations can be determined systematically.