In this work, we propose virtual memory environments for instruction scratchpad memory (SPM). Our approach consists of two mechanisms. One is for the embedded systems with no memory management unit (MMU) and the other is for the systems with an MMU. Both are based on demand paging and postpass optimization techniques.

For the systems with no MMU, the virtual memory is implemented purely by software. An SPM manager routine loads required code segments into the SPM on demand at runtime. The code mapping is determined by solving mixed integer linear programming formulation that approximates our demand paging technique. We increase the effectiveness of demand paging by extracting from functions natural loops that are smaller in size and have a higher instruction fetch count. The postpass optimizer analyzes the object files of an application and transforms them into an application binary image that enables demand paging to the SPM. 

On the other hand, for the systems with an MMU, we propose a dynamic scratchpad memory allocation strategy targeting a horizontally partitioned memory subsystem. The memory subsystem is equipped with an MMU, and the physically addressed SPM is mapped into the virtual address space. A small instruction minicache is added to further reduce energy consumption and improve performance. Using the MMU¡¯s page fault exception mechanism, we track page accesses and copy frequently executed code sections into the SPM before they are executed. Because the minimal transfer unit between the external memory and the SPM is a single memory page, good code placement is of great importance for the success of our method. We discuss code grouping techniques and also analyze the effect of the minicache on execution time and energy consumption.

We evaluate our techniques on several embedded benchmark applications and compare the results to those of a processor core with an instruction cache. The experimental results show that our techniques are quite effective in reducing energy consumption and improving performance, and the SPM can replace the instruction cache.