In non-preemptive embedded systems, precise timing guarantees can be computed and the overall performance of the system simply consists of the performances of all tasks, viewed independent from each other.
In preemptive systems, the situation gets more complex. The overall performance is also determined by the interference of the tasks during preemption. Hereby especially the interference on the cache matters.

We propose a new method to analyze and optimize the task interference on the cache already during compile time. Therefor, we optimize the memory placement of the systems' tasks. On the hand hand, we minimize the number of cache misses to optimize the performance and on the other hand, we try to ensure the persistence of cache-lines of hard real-time tasks during a single run of a task. If it is not possible to ensure cache persistence, we can classify cache-lines as safe or unsafe and use this information to derive timing guarantees also valid in case of preemption.