Verification is an important aspect of chip design with about half of
total engineering time spent on it. In particular, the design and
maintenance of the test benches that are required for verification make
this an expensive step in the overall chip design. The expense is
further compounded by the observation that the test bench is not part of
the functional design that forms the eventual product. System-level
simulation can be employed to mitigate these expenses, as the designed
component is tested by embedding it into a system model. Because of the
different tools typically used for the system design and logic
emulation, at present, a co-simulation approach to facilitate the
system-level verification appears to be the only feasible solution.
Co-simulation has to address an important difference in simulation
technologies that are typically used in the respective tools. Where
system-level design tools often employ a time-driven simulation
approach, logic-emulation tools tend to be based on event-driven
simulation methods. This presentation discusses the combination of
event-driven and time-driven simulation and identifies the issues that
arise in such a hybrid approach.