The talk will look at the issues of implementing complex DSP systems on heterogeneous platforms comprising GPPs, DSP processors and FPGAs. The emphasis is to develop a high level design flow that allows optimisation to be carried out in a top-down manner but which can efficiently exploit IP cores that will have pre-determined features e.g. latency. The talk will describe how dataflow has been used and then modified to allow this to happen. A design example of a normalised lattice filter will be presented. Some conclusions and future work will be outlined along with application to reconfigurable systems.