Traditionally, FPGAs are deployed due to their flexibility to change the application over time. Newly developed architectures can be reconfigured within one clock cycle so that components of a device can re-used within a single application promising a better price-performance ratio. The reconfiguration keeping pace with the execution yields an additional degree of freedom that constitutes a new principle of reconfiguration. We name this principle processor-like reconfiguration. A silicon-proven processor-like reconfigurable architecture is NEC's Dynamically Reconfigurable Processor Architecture (DRP) which we use to validate parts of our research.

In our current work, it is evaluated how processor-like reconfiguration can be exploited by a high-level compiler and which architectural resources are needed for an efficient mapping of applications. To accomplish this, the CRC model (Configurable Reconfigurable Core) was developed as a general model for processor-like reconfigurable architectures. The features of the CRC model are modified according to the requirements imposed by mapping applications onto it. For this application mapping, well known techniques from C-based hardware synthesis and from compilers for VLIW processors are deployed. Instances of the CRC model can be synthesized and analyzed at the gate-level for a detailed assessment including a comparison to FPGAs. First results on mapping a real-world example from visual computing have shown considerable advantages of processor-like reconfigurable architectures compared to FPGAs.

Besides the fast reconfiguration mechanism for the functionality, we extend the concept of processor-like reconfiguration for voltage sources. The power dissipation in each time step, the total energy consumption as well as the energy-delay product can be reduced enormously by temporal-spatial voltage assignment. In contrast to other voltage scaling approaches no adaptation of the clock frequency is required.

In particular for coarse-grained reconfigurable architectures, a designer must consider how each application makes use of the provided architectural resources. Therefore, application-domain specific architectures are developed taking into account various techniques that may be used by the compiler.