Current network devices have to keep up with increasing bandwidth, growing complexity and rapid changes in network protocols and applications. Conventional hardware systems cannot meet with the required flexibility. Software-based solutions or even hybrid systems such as network processors that combine hardware and software solutions do not achieve the  performance requirements. Hence, other architectural solutions have to be found in order to cope with the increasing data rates of network applications.
We address this problem with DynaCORE, an application specific coprocessor for offloading computationally intensive tasks from a network processor. The system-on-chip architecture is based on an adaptable network-on-chip which allows the dynamic replacement of hardware modules as well as the adaptation of the on-chip communication structure. The exploitation of partial dynamic reconfiguration allows a rapid adaptation towards modified system 
behaviors. The design of DynaCORE, its performance requirements as well as its hardware structure are introduced in this presentation.