Reconfigurable hardware has been successfully deployed for  accelerating computationally demanding applications. While providing enormous flexibility dynamically reconfiguring applications suffer from the large reconfiguration overhead inflicted by contemporary architectures. We propose to design multi-level reconfigurable architectures  that can help to reduce this reconfiguration overhead by introducing different levels of reconfiguration, each streamlining the capabilities of its lower levels. 

In this talk we present formal models for multi-level reconfiguration. For the switch model were reconfigurable units are seen a cost model that measures the reconfiguration costs are defined. Based on this cost model we study the complexity of several optimization problems.  One problem is to find for a given algorithm the optimal time steps when reconfiguration operations should be done of the different levels. Other problems are to find the optimal number of reconfiguration levels and the best granularity for reconfiguration of on the different levels.  We present algorithms to solve this problems and present results for several applications.