On this presentation a multi-board, multi-FPGA hard-
ware/software architecture, for computation intensive, high
resolution (2048x2048 pixels), real-time (24 frames per sec-
ond) digital Film processing. It is based on Xilinx Virtex-
II Pro FPGAs, large SDRAM memories for multiple frame
storage and a PCI express communication network. The ar-
chitecture reaches record performance running a complex
noise reduction algorithm including a 2.5 dimensions DWT
and a full 16x16 motion estimation at 24 fps requiring a
total of 203 Gops/s net computing performance and a to-
tal of 28 Gbit/s DDR-SDRAM frame memory bandwidth.
To increase design productivity and yet achieve high clock
rates (125MHz), the architecture combines macro com-
ponent configuration and macro level floorplanning with
weak programmability using distributed microcoding.