The first superscalar architectures have been designed to allow instruction level parallelism without involving the programmer or the compiler into the parallelization process. Within an instruction window the issue logic schedules instructions by the dataflow principle and maps them on unemployed functional units which are suitable to perform the calculation as indicated by the opcode. The maximum total of concurrently executable instructions is then only restricted by the size of the instruction window and by the total of functional units. With this execution scheme it is possible to build processors with identical instruction sets but differently equipped execution stages. 

As the execution stages can be differently equipped with functional units without affecting the executability of the code they are an interesting subject for reconfiguration.

In the presentation a superscalar processor is proposed that contains such a reconfigurable execution stage together with an extended issue logic and a configuration management unit. This unit controls the reconfiguration of the execution stage.  It decides whether the current configuration of the execution stage is suitable for the upcoming computations or not. If it rates another configurations better than the current configuration of the execution stage, it can trigger the reconfiguration procedure.

Together with the processor architecture some simulation an benchmarking results are shown.