The last decades have experienced a continuous growth in the performance of multiprocessor according to the Moore law. This increase in performance is mainly due to two main reasons: the clock frequency that keep growing and efficient use von Instruction Level Parallelism (ILP). With the difficulty to continuously improve the clock frequency as well as the ILP has investigation, Chip multiprocessor have begun to appear as an alternative to increase performance through processor level parallelisms. Most of the solutions proposed and developed are mainly SMP-based. Furthermore the architecture is fixed, thus limiting the architectural flexibility. With the growing capacity of FPGAs, it is more and more possible to place several soft or hardcore processors working in parallel on a given FPGA. Moreover, the flexible logic allows for the runtime adaptivity of applications by exchanging hardware accelerator.
In this talk, we present the on going work in adaptive on-chip multiprocessor at the University of Kaiserslautern.