ADRES is a new coarse grain reconfigurable processor device, that is fully programmable in C. ADRES supports design-time and runtime reconfigurability for a broad range of multi-mode embedded applications, such as such as MPEG-2, MPEG-4, AVC/H.264 or Scalable Video Coding.

To address the challenges of multimode operations, ADRES provides improved power efficiency and performance within acceptable area constraints. ADRES targets a power efficiency of at least 40 MOPS/mW while being able to handle a peak performance of 20 GOPS, requirements that clearly go beyond the specs of any state-of-the-art core.

The ADRES array processor is a flexible template instead of a concrete instance. An architecture description language is developed to specify different ADRES instances with full compiler support. A script-based technique allows a designer to easily generate different instances by specifying different values for the communication topology, supported operation set, resource allocation and timing of the target architecture. Together with a retargetable simulator and compiler, this toolchain allows for architecture exploration and development of application domain specific processors.

ADRES supports a VLIW-like programming model with a pure VLIW mode for legacy code, and an array mode with very high dataflow-parallelism for the processing of compute intensive loops. In parallel to ADRES, an C-compiler that can create seamless code for both modes using modulo scheduling techniques and that is based on IMPACT was developed. The compiler takes automatically care of all necessary data transfers between the two modes.

Several applications from the wireless and from the multimedia domain have been mapped on ADRES. As an example, an ADRES based system can perform AVC decoding in CIF resolution with less then 50 MHz on a 4x4 array on compiled C-Code. MPEG-2 CIF decoding needs only 27 MHz. Several key benchmark kernel loops have been mapped on ADRES and the results show that ADRES can extend the performance of state-of-the Art  VLIW DSPs by a factor of 7, which makes ADRES an attractive alternative to multi-core DSP solutions.

Synthesis results show, that such an ADRES core consumes less then 2 mm2 in 90nm technology and can run with more then 500 MHz. Considering that the array size can be further increased to 8x8 or beyond, ADRES offers significant room for further speedup.

ADRES significantly beats a state-of-the art DSP, like the TI C64x, with fewer resources and at comparable power consumption. At the same time ADRES offers performance and power scalability by using more resources and larger array sizes. Therefore, ADRES based designs will reduce the need for multi-processor solutions.